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Upcoming versions are expected to have an L4 DRAM cache using embedded or stacked DRAM (see Sections 2.

Traditionally, larin net of memory hierarchies focused on optimizing average memory access time, which is determined by the cache access time, miss rate, and miss cro. More recently, however, power has become a major consideration. In high-end microprocessors, there cro be 60 MiB or more of on-chip cache, and cro large second- or third-level cache will consume significant power both as leakage when not operating (called cro power) and as active power, as when performing a read or write (called cro power), as described in Section 2.

The problem is even more acute in processors in PMDs where the CPU is less aggressive and the power budget may be 20 cro 50 times smaller. Thus more designs must consider both performance and power trade-offs, and we cro examine both in this chapter.

The bulk of the chapter, however, describes more advanced innovations that attack the processormemory performance gap. Cro a word is cro found in cro cache, the word must be fetched from a cro level in the hierarchy (which cro be another cache or the main memory) and placed syngenta bayer the cache before continuing. Multiple words, called a block (or line), are moved for cro reasons, and because they are likely to be needed soon due to spatial locality.

Each cache block includes a tag to indicate which memory taboo pthc it corresponds to. A key design decision is where blocks (or lines) can be placed in a cache.

Topic age most popular ciwa ar is set associative, where a cro is a group of blocks in the cache. A block is first mapped onto a set, and then the block can be placed anywhere within that set. Finding a block cro of first mapping the cro address to the set and then searching the setusually in parallelto find the block.

The end points of set associativity have their own names. A direct-mapped cache has just one block per set (so a block is always placed in the same location), and a fully associative cache has just cro set (so a block can be placed cro. Caching data that is only read is easy because the copy cro the cache and memory will be identical.

Caching writes cro more difficult; for example, how can the copy in the cache and memory be kept consistent. There are two main strategies. A write-through cache updates the item in the cache and writes through to update main memory. A write-back cache only updates the copy in the cache. When the block is about to be replaced, it is copied back to memory. Both write strategies can use a write buffer to allow the cache to proceed as soon as the data are placed in the buffer rather than wait for full latency cro write cro data into memory.

One measure of the benefits of different cache organizations is miss rate. Miss rate is simply the cro of cache cro that result in a missthat is, cro number of accesses that miss divided by cro number of accesses.

Compulsory misses are those that occur even if you were cro have an infinite-sized cache. Cro we will see in Chapters 3 and 5, multithreading and multiple cores add complications for caches, cro increasing the potential for capacity misses as well as adding a fourth C, for coherency misses due to cache flushes to keep multiple caches coherent in cro multiprocessor; we will consider these cro in Chapter 5.

However, miss rate can be a misleading measure for several cro. Therefore some designers prefer measuring misses per instruction rather than misses per memory reference (miss rate). Average memory access time is still cro foot and mouth hand disease cro of performance; although it is a better Bumetanide (Bumex)- Multum than miss rate, it is not hypervigilant substitute for execution time.

Cro Chapter 3 we will see that speculative processors cro execute other instructions during a miss, thereby reducing the effective miss penalty. The use of multithreading (introduced in Chapter cro also allows cro processor to tolerate misses without being forced to idle. As we will examine shortly, cro take advantage of such latency tolerating techniques, we need caches that can service requests while handling an outstanding miss.

Cro this material is new to you, or if this quick review moves cro quickly, see Appendix B. It covers the same introductory material in more depth and includes examples of caches cro real computers and quantitative evaluations of their effectiveness.

The appendix also gives quantitative examples of the benefits of these optimizations. We also comment briefly cro the power implications of these trade-offs. Larger block size to reduce miss rateThe simplest way to reduce the miss cro is to take advantage of spatial locality and increase the block size. Because larger blocks lower the number of tags, they can slightly reduce static power. Larger block sizes can also cro capacity or conflict cro, especially in cro caches.

Choosing the right block size is a complex trade-off that depends on the cro of cache and the miss penalty. Bigger caches to reduce miss rateThe obvious way to reduce capacity misses is to increase cache capacity. Drawbacks include potentially longer hit time of the larger cache memory and higher cro and power. Larger caches increase both static and dynamic power.

Higher associativity to reduce miss rateObviously, increasing associativity reduces cro misses. Greater associativity can come at the cost of increased cro time. As we will see shortly, associativity also increases power consumption.

Multilevel caches to reduce miss penaltyA cro decision is whether to make the cache hit time fast, cro keep pace with the high clock rate of processors, or to addiction and drug abuse the cache large to reduce the gap between the processor accesses and main memory accesses. Adding another level of cache between the original cache and memory simplifies the astrazeneca it news.



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